Principal SoC Design Engineer / SoC Lead

Neurophos
San Mateo, California, United States
Full Time
On Site
Senior
USD 225,000 – 300,000
Engineering Industrial & Engineering

Posted 1 day ago

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Excellent 4.7

Job summary

The role involves leading the integration of complex chip designs, making cross-domain decisions in areas such as system functionality, DFT, power, timing, and interconnect architecture. The candidate will work closely with various engineering teams across domains, be hands-on at every level, and help scale the design organization through hiring and mentoring, with a focus on advanced-node, high-speed, high-bandwidth, and large-scale semiconductor designs.

Responsibilities

Lead the integration of the full chip or major subsystems while making cross-domain technical decisions regarding DFT, power, timing, and interconnect architecture. Collaborate with system architects, RTL, and physical design teams to resolve system-level tradeoffs and mentor engineering staff.

Qualifications

chip design data-fabric high-speed interconnect interconnect architecture microarchitecture physical design power management RTL timing closure verification

Requires principal-level technical leadership experience at a semiconductor or systems company with multiple full-chip tapeouts. Candidates must demonstrate deep expertise in CPU or high-speed interconnect design and experience with advanced process nodes.

English

Benefits

  • Health insurance
  • HSA contributions
  • Unlimited PTO
  • 401(k) matching
  • Stock options
  • Dental insurance
  • Vision insurance
  • Life insurance
  • Hospital insurance
  • Critical illness insurance
  • Accident insurance

Company

Neurophos

Neurophos

linkedin
Computer Hardware
Location
San Mateo, California, United States

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Excellent 4.7
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