Sr. Engineer, CPU RTL Design

Tenstorrent
Santa Clara, California, United States
Full Time
Hybrid
Senior
USD 100,000 – 500,000
Engineering Information Technology Telecommunications

Posted 2 days ago

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Excellent 4.7

Job summary

Join Tenstorrent's CPU design team as a Sr. Engineer to define and implement RTL for high-performance RISC-V CPUs. Collaborate with various teams to deliver functional, timing, and power-efficient CPU designs, focusing on microarchitecture, RTL coding, debugging, and optimization.

Responsibilities

Define and implement RTL for high-performance RISC-V CPUs, focusing on microarchitecture development for specific CPU blocks. Collaborate with DV, PD, and performance teams to ensure functional, timing, and power convergence.

Qualifications

CPU microarchitecture Debugging RTL/logic Microarchitecture definition Performance analysis Power analysis RTL coding Simulation Synthesis Verilog VHDL

Requires expertise in CPU microarchitecture components such as Rename, Scheduler, and Cache, along with proficiency in Verilog/VHDL. Candidates must be skilled in debugging RTL across multiple hierarchies and performing performance-driven trade-off analysis.

English

Benefits

Competitive Compensation Package

Company

Tenstorrent

Tenstorrent

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Computer Hardware Manufacturing
Location
Santa Clara, California, United States

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Excellent 4.7
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