Senior Digital Verification Engineer

Efficient Computer
San Jose, California, United States
Full Time
On Site
Senior
USD 160,000 – 210,000
Bachelor Degree
Technology Industrial & Engineering

Posted 2 days ago

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Excellent 4.7

Job summary

Experienced Design Verification Engineer responsible for driving the functional verification of complex SoC/IP designs, from specification to tapeout, focusing on high-level verification methodology, debug, scripting, and automation in a fast-paced semiconductor environment.

Responsibilities

Drive the functional verification of complex SoC/IP designs from specification through tapeout. Collaborate with the team to shape product processes and ensure high-quality verification sign-off.

Qualifications

AI/ML C/C++ Coverage closure Debug Formal verification Power aware verification Python Software/Firmware testing SystemVerilog UVM

Requires a Bachelor's, Master's, or PhD in Electrical or Computer Engineering with over 10 years of experience in ASIC/SoC verification. Candidates must possess deep expertise in UVM, SystemVerilog, and C/C++ with a proven track record of tapeout success.

English

Benefits

  • 401k Match
  • Company-paid benefits
  • Equity program
  • Paid parental leave
  • Flexibility

Company

Efficient Computer

Efficient Computer

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Computer Hardware Manufacturing
Location
San Jose, California, United States

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Excellent 4.7
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