Lead Digital Verification Engineer

Efficient Computer
San Jose, California, United States
Full Time
On Site
Senior
USD 200,000 – 230,000
Bachelor Degree
Engineering Industrial & Engineering

Posted 1 day ago

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Excellent 4.7

Job summary

Seeking an experienced Design Verification Lead to oversee the functional verification of complex SoC/IP designs, define verification strategies, and lead a team to ensure quality and readiness for product tapeout. Must have expertise in UVM, SystemVerilog, debug, and SoC architecture with leadership experience.

Responsibilities

The Lead Digital Verification Engineer will define the end-to-end verification strategy across block, subsystem, and full-chip levels, authoring plans and architecting scalable UVM-based testbench environments. Key duties include driving constrained-random stimulus, closing functional coverage, deploying assertions, leading full-chip verification tasks like power-on reset and multi-block interactions, and owning the bug lifecycle.

Qualifications

constrained-random coverage closure debugging Python SoC architecture SystemVerilog Tcl UVM verification planning verification strategy

Candidates must possess 10+ years in ASIC/SoC design verification, including at least 3 years in a lead role owning strategy and sign-off, with a Bachelor's or higher degree in a related engineering field. Required technical depth includes mastery of UVM, advanced SystemVerilog, proven coverage closure on complex SoCs, strong debugging skills, and proficiency in scripting languages like Python.

English

Benefits

  • 401K Match
  • Company-paid Benefits
  • Equity Program
  • Paid Parental Leave
  • Flexibility

Company

Efficient Computer

Efficient Computer

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Computer Hardware Manufacturing
Location
San Jose, California, United States

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Excellent 4.7
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